| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-10-25T06:40:17Z |
|
| dc.date.available |
2023-10-25T06:40:17Z |
|
| dc.date.issued |
2015-10 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/abstract/document/7258333 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12613 |
|
| dc.description.abstract |
In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5× improvement in the electrostatic discharge robustness are reported experimentally. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
CMOS technologies |
en_US |
| dc.subject |
Device-circuit codesign |
en_US |
| dc.subject |
Drain-extended MOSFET (DeMOS) |
en_US |
| dc.subject |
Electrostatic discharge (ESD) |
en_US |
| dc.subject |
Shallow-trench-isolation (STI) |
en_US |
| dc.subject |
System-on-chip (SoC) |
en_US |
| dc.title |
Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness |
en_US |
| dc.type |
Article |
en_US |