| dc.contributor.author | Rao, V. Ramgopal | |
| dc.date.accessioned | 2023-10-26T04:27:51Z | |
| dc.date.available | 2023-10-26T04:27:51Z | |
| dc.date.issued | 2014-11 | |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/6895292 | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12624 | |
| dc.description.abstract | The metal-gate granularity-induced threshold voltage (V T ) variability and V T mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode V T variability are analyzed. The V T mismatch study predicts lower mismatch figure of merit (A VT ) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Gate-all-around (GAA) | en_US |
| dc.subject | Metal-gate granularity (MGG) | en_US |
| dc.subject | Silicon nanowire FET | en_US |
| dc.subject | Work function (WF) | en_US |
| dc.title | Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs | en_US |
| dc.type | Article | en_US |
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