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DC Compact Model for SOI Tunnel Field-Effect Transistors

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-10-26T10:16:16Z
dc.date.available 2023-10-26T10:16:16Z
dc.date.issued 2012-10
dc.identifier.uri https://ieeexplore.ieee.org/document/6253238
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12648
dc.description.abstract A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage V th , charge in the channel Q , gate capacitance C G , drain current I DS , subthreshold swing S , transconductance g m , and output conductance g DS , have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Band-to-band (BTB) tunneling en_US
dc.subject Compact model en_US
dc.subject Complementary metal–oxide–semiconductor (CMOS) en_US
dc.subject Low standby power (LSTP) en_US
dc.subject Metal–oxide–semiconductor field-effect transistor (MOSFET) en_US
dc.title DC Compact Model for SOI Tunnel Field-Effect Transistors en_US
dc.type Article en_US


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