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A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-10-27T11:04:44Z
dc.date.available 2023-10-27T11:04:44Z
dc.date.issued 2010-06
dc.identifier.uri https://ieeexplore.ieee.org/abstract/document/5446394
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12685
dc.description.abstract For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Bulk fin-shaped field-effect transistor (FinFET) en_US
dc.subject Electrothermal modeling en_US
dc.subject Fin-shaped field-effect transistor (FET) (FinFET) en_US
dc.subject Width quantization en_US
dc.title A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance en_US
dc.type Article en_US


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