dc.contributor.author |
Rao, V. Ramgopal |
|
dc.date.accessioned |
2023-10-28T03:57:55Z |
|
dc.date.available |
2023-10-28T03:57:55Z |
|
dc.date.issued |
2010-02 |
|
dc.identifier.uri |
https://ieeexplore.ieee.org/document/5350732 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12691 |
|
dc.description.abstract |
In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Drain-extended MOSFET (DeMOS) |
en_US |
dc.subject |
Hot carrier |
en_US |
dc.subject |
Input/output |
en_US |
dc.subject |
Lightly doped drain MOS (LDDMOS) |
en_US |
dc.subject |
Mixed-signal |
en_US |
dc.subject |
Reduced surface field (RESURF) |
en_US |
dc.title |
Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices |
en_US |
dc.type |
Article |
en_US |