dc.contributor.author |
Rao, V. Ramgopal |
|
dc.date.accessioned |
2023-10-30T09:23:31Z |
|
dc.date.available |
2023-10-30T09:23:31Z |
|
dc.date.issued |
2005-12 |
|
dc.identifier.uri |
https://ieeexplore.ieee.org/document/1546322 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12726 |
|
dc.description.abstract |
A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Analog/mixed-signal circuits |
en_US |
dc.subject |
Circuit lifetime |
en_US |
dc.subject |
Negative bias temperature instability (NBTI) |
en_US |
dc.subject |
pMOSFET degradation |
en_US |
dc.subject |
Threshold-voltage shift |
en_US |
dc.title |
NBTI degradation and its impact for analog circuit reliability |
en_US |
dc.type |
Article |
en_US |