Abstract:
In this paper we look at the effect of
Fringe-Enhanced-Barrier-lowering (FEBL) for high-
K dielectric MOSFETs and the dependence of
FEBL on various technological parameters (spacer
dielectrics, overlap length, dielectric stack, S/D
junction depth and dielectric thickness). We show
that FEBL needs to be contained in order to maintain
the performance advantage with scaled high-K
dielectric MOSFETs. The degradation in high-K
dielectric MOSFETs is also identified as due to the
additional coupling between the drain-to-source that
occurs through the gate insulator, when the gate
dielectric constant is significantly higher than the
silicon dielectric constant. The technology parameters
required to minimize the coupling through the high-
K dielectric are identified. It is also shown that gate
dielectric stack with a low-K material as bottom layer
(very thin SiO2 or oxy-nitride) will be helpful in
minimizing FEBL. The circuit performance issues
with high-K MOS transistors are also analyzed in this
paper. An optimum range of values for the dielectric
constant has been identified from the delay and the
energy dissipation point of view. The dependence of
the optimum K for different technology generations
has been discussed. Circuit models for the parasitic
capacitances in high-K transistors, by incorporating
the fringing effects, have been presented.