| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-10-31T06:18:27Z |
|
| dc.date.available |
2023-10-31T06:18:27Z |
|
| dc.date.issued |
2002-06 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/1003752 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12748 |
|
| dc.description.abstract |
Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V/sub T/ adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
MOSFETs |
en_US |
| dc.subject |
Semiconductor device reliability |
en_US |
| dc.subject |
Semiconductor device doping |
en_US |
| dc.subject |
Ion implantation |
en_US |
| dc.subject |
Hot carriers |
en_US |
| dc.title |
Optimization and realization of sub-100-nm channel length single halo p-MOSFETs |
en_US |
| dc.type |
Book |
en_US |