Abstract:
The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determined using a novel charge pumping technique. Detailed post-stress interface characterization shows reduced interface-trap buildup and lesser drain current degradation in LAC MOSFETs compared to the CON device, for stressing at different times and drain biases and for all channel lengths down to 100 nm. The interface-trap profile parameters (peak magnitude and spread) have been correlated to drain current degradation as function of stress drain bias and time. It is shown that with increased stress drain bias and time, both the peak and spread of the interface-trap profiles increase, but at different rates. While the peaks evolve identically for CON and LAC MOSFETs, the spreads do not, which is shown to affect the rate of the resulting transconductance degradation differently. Device simulations show a lower peak lateral electric field in LAC MOSFETs compared to CON devices, which is responsible for the observed reduction in hot-carrier degradation in such devices.