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Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-10-31T08:56:13Z
dc.date.available 2023-10-31T08:56:13Z
dc.date.issued 2000-04
dc.identifier.uri https://ieeexplore.ieee.org/document/830995
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12759
dc.description.abstract The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N/sub it/ and N/sub ot/ profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N/sub it/ and N/sub ot/ profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N/sub it/ generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N/sub it/ profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject MOSFETs en_US
dc.subject Interface states en_US
dc.subject Semiconductor device measurement en_US
dc.title Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs en_US
dc.type Article en_US


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