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Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-10-31T09:24:11Z
dc.date.available 2023-10-31T09:24:11Z
dc.date.issued 1998-05
dc.identifier.uri https://ieeexplore.ieee.org/document/670162
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12767
dc.description.abstract In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Plasma applications en_US
dc.subject Plasma materials processing en_US
dc.subject Plasma devices en_US
dc.subject Plasma simulation en_US
dc.subject Etching en_US
dc.subject Electron traps en_US
dc.title Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices en_US
dc.type Article en_US


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