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On the breakdown physics of trench-gate drain extended NMOS

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-11-02T07:18:59Z
dc.date.available 2023-11-02T07:18:59Z
dc.date.issued 2015-06
dc.identifier.uri https://ieeexplore.ieee.org/document/7285240
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12805
dc.description.abstract In this work, two drain extended NMOS (DeNMOS) devices, one with only planar gate and another with both planar gate and gate in a trench under the gate-drain overlap region (called trench-gate DeNMOS) are investigated. The latter device shows improved ON-state performance due to greater spacecharge control with addition of trench gate. The OFF-state breakdown physics is also compared with conventional DeNMOS device. Due to greater field spreading in the trench-gate device under OFF-state conditions, a distinct base-push effect is not observed, unlike conventional device. The oxide reliability in trench-gate device improves with an additional offset in the drift region. Therefore, the trench-gate DeNMOS can be used as an alternative to improve input/output (I/O) device performance and reliability in advanced system-on-chip (SoC) applications. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Logic gates en_US
dc.subject Electric breakdown en_US
dc.subject Semiconductor process modeling en_US
dc.subject Impact ionization en_US
dc.title On the breakdown physics of trench-gate drain extended NMOS en_US
dc.type Article en_US


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