Circuit Optimization at 22nm Technology Node

Abstract

With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit performance. To miti-gate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, Fin FET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device, since, such Fin FET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the performance enhancement with such Fin FET Device for Mux Circuit, and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).