| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-11-03T09:07:38Z |
|
| dc.date.available |
2023-11-03T09:07:38Z |
|
| dc.date.issued |
2009 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/4796530 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12844 |
|
| dc.description.abstract |
A novel table-based environment for automatic design and optimization of FinFET circuits is demonstrated. A new accurate look-up table (LUT) technique is implemented in a circuit simulator and integrated with particle swarm optimization algorithm for efficient circuit designs in novel devices. Op-amp circuits are designed and optimized to demonstrate the accuracy and usefulness of the proposed platform. Further, it is shown that the proposed design methodology can take into account variations in process, supply voltage, and temperature |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Design optimization |
en_US |
| dc.subject |
Table lookup |
en_US |
| dc.subject |
Integrated circuit technology |
en_US |
| dc.subject |
Design methodology |
en_US |
| dc.subject |
Voltage |
en_US |
| dc.subject |
Temperature |
en_US |
| dc.title |
Automated design and optimization of circuits in emerging technologies |
en_US |
| dc.type |
Article |
en_US |