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Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-11-04T06:24:46Z
dc.date.available 2023-11-04T06:24:46Z
dc.date.issued 2006
dc.identifier.uri https://ieeexplore.ieee.org/document/1581430
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12859
dc.description.abstract MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Tutorial en_US
dc.subject CMOS technology en_US
dc.subject Analog circuits en_US
dc.subject CMOS analog integrated circuits en_US
dc.subject CMOS digital integrated circuits en_US
dc.title Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies en_US
dc.type Article en_US


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