The influence of process variations on the Halo MOSFETs and its implications on the analog circuit performance

Abstract

Lateral Asymmetric Channel (LAC) and Double Halo (DH) MOSFETs have been reported to exhibit excellent properties for mixed signal CMOS applications. In this work, the effect of process variations such as gate oxide thickness, implantation parameters, and channel length are systematically investigated on the device and analog circuit performance for all these technologies. The performance parameters of LAC and DH differential amplifiers and current mirror circuits are evaluated, using mixed-mode simulations, as a function of process induced mismatch. Our simulation results on differential amplifiers and current mirrors show that, an identical V, mismatch in CON, DH, and LAC devices results in a lower variation in the circuit parameters for LAC technologies. It is found that, for a specified circuit parameter variation, almost a 25% higher V, mismatch is tolerable with LAC technologies as compared to the CON technologies.