| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-11-06T09:48:58Z |
|
| dc.date.available |
2023-11-06T09:48:58Z |
|
| dc.date.issued |
2003 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/1197802 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12874 |
|
| dc.description.abstract |
The effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (V/sub CG/) and is insensitive to changes in drain bias (V/sub D/) CHISEL degradation is insensitive to changes in both V/sub CG/, and V/sub D/. Furthermore, CHISEL always shows lower degradation when compared to CHE under identical bias and similar programming time. The possible physical mechanisms responsible for the above behavior are clarified by using full band Monte-Carlo simulations. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Channel hot electron injection |
en_US |
| dc.subject |
EPROM |
en_US |
| dc.subject |
Degradation |
en_US |
| dc.subject |
Nonvolatile memory |
en_US |
| dc.subject |
Integrated circuit reliability |
en_US |
| dc.subject |
Energy Consumption |
en_US |
| dc.subject |
Threshold voltage |
en_US |
| dc.title |
Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs |
en_US |
| dc.type |
Article |
en_US |