| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-11-06T10:06:59Z |
|
| dc.date.available |
2023-11-06T10:06:59Z |
|
| dc.date.issued |
2003-09 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/1256933 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12875 |
|
| dc.description.abstract |
The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Reliability engineering |
en_US |
| dc.subject |
EPROM |
en_US |
| dc.subject |
Doping |
en_US |
| dc.subject |
Integrated circuit technology |
en_US |
| dc.subject |
Design engineering |
en_US |
| dc.title |
The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs |
en_US |
| dc.type |
Article |
en_US |