| dc.contributor.author |
Rao, V. Ramgopal |
|
| dc.date.accessioned |
2023-11-06T10:56:43Z |
|
| dc.date.available |
2023-11-06T10:56:43Z |
|
| dc.date.issued |
2011-02 |
|
| dc.identifier.uri |
https://link.springer.com/article/10.1557/PROC-716-B4.18 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12880 |
|
| dc.description.abstract |
In this paper we discuss a new method for measuring border trap density (Nbt) in sub-micron transistors using the hysteresis in drain current. We have used this method to measure Nbt in jet Vapour Deposited (JVD) Silcon Nitride transistors (MNSFETs). We have extended this method to measure the energy and spatial distribution of border traps in these devices. The transient drain current varies linearly with logarthmic time. This suggests that tunneling is the dominant charge exchange mechanism of border traps. The pre-stress energy distribution is uniform whereas poststress energy distribution shows a peak near the midgap. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
Springer |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Jet Vapour Deposited (JVD) |
en_US |
| dc.subject |
Silcon Nitride transistors (MNSFETs) |
en_US |
| dc.title |
Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET |
en_US |
| dc.type |
Article |
en_US |