| dc.contributor.author | Rao, V. Ramgopal | |
| dc.date.accessioned | 2023-11-07T04:08:27Z | |
| dc.date.available | 2023-11-07T04:08:27Z | |
| dc.date.issued | 2002 | |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/1025667 | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12883 | |
| dc.description.abstract | In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Boron | en_US |
| dc.subject | Wire | en_US |
| dc.subject | CMOS technology | en_US |
| dc.subject | Grain size | en_US |
| dc.subject | CMOS process | en_US |
| dc.subject | Tungsten | en_US |
| dc.title | Suppression of boron penetration by hot wire CVD polysilicon | en_US |
| dc.type | Article | en_US |
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