Abstract:
The potential impact of high permittivity gate
dielectrics on the circuit performance is
studied over a wide range of gate dielectrics
using 2-Dimensional device and monte-carlo
simulations. It is found that there is a decrease
in parasitic outer fringe capacitance, gate to
channel capacitance and an increase in
internal fringe capacitance, when the
conventional silicon dioxide is replaced by
high-K gate dielectrics. The lower parasitic
outer fringe capacitance is beneficial in
reducing the circuit delay, while an increase in
internal fringe capacitance and decrease in
gate to channel capacitance will degrade the
gain, power dissipation and noise margin of
the circuit. Also, from the circuit point of view,
at the 70nm technology generation, the
presence of an optimum Kgate for different subthreshold
leakage currents has been identified