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Study of Degradation in Channel Initiated Secondary Electron Injection Regime

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-11-07T07:07:56Z
dc.date.available 2023-11-07T07:07:56Z
dc.date.issued 2001-09
dc.identifier.uri https://ieeexplore.ieee.org/document/1506640
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12891
dc.description.abstract This paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Degradation en_US
dc.subject Current measurement en_US
dc.subject Nonvolatile memory en_US
dc.subject MOSFETs en_US
dc.subject Hot carriers en_US
dc.subject Charge pumping en_US
dc.title Study of Degradation in Channel Initiated Secondary Electron Injection Regime en_US
dc.type Article en_US


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