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Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-11-07T09:04:06Z
dc.date.available 2023-11-07T09:04:06Z
dc.date.issued 2001
dc.identifier.uri https://ieeexplore.ieee.org/document/902703
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12893
dc.description.abstract A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Optimization en_US
dc.subject MOSFETs en_US
dc.subject Molecular beam epitaxial growth en_US
dc.subject Medical simulation en_US
dc.subject Doping profiles en_US
dc.subject Electric variables en_US
dc.title Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering en_US
dc.type Article en_US


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