dc.contributor.author | Rao, V. Ramgopal | |
dc.date.accessioned | 2023-11-07T10:19:17Z | |
dc.date.available | 2023-11-07T10:19:17Z | |
dc.date.issued | 1999 | |
dc.identifier.uri | https://ieeexplore.ieee.org/document/799349 | |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12900 | |
dc.description.abstract | Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Silicon compounds | en_US |
dc.subject | MOSFETs | en_US |
dc.subject | Transconductance | en_US |
dc.subject | Hot carriers | en_US |
dc.subject | Degradation | en_US |
dc.title | 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric | en_US |
dc.type | Article | en_US |
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