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Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

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dc.contributor.author Rao, V. Ramgopal
dc.date.accessioned 2023-11-07T11:11:33Z
dc.date.available 2023-11-07T11:11:33Z
dc.date.issued 1998-10
dc.identifier.uri https://ieeexplore.ieee.org/document/723137
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12906
dc.description.abstract SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject MOSFETs en_US
dc.subject Los Angeles Council en_US
dc.subject Threshold voltage en_US
dc.subject Electronic devices en_US
dc.subject Very large scale integration en_US
dc.subject Amorphous materials en_US
dc.subject Silicidation en_US
dc.title Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology en_US
dc.type Article en_US


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