| dc.description.abstract |
In recent times, the idea of hardware accelerators has gained a lot of attraction, which are implemented on Field Programmable Gate Arrays (FPGAs) to speed-up the com-monly used software functions. The interest increased even more when Xilinx released Python Productivity for Zynq (PYNQ), a framework offering a much easier design methodology for such accelerators. In this study, we have designed a hardware accel-erator for a Fast Fourier Transform (FFT) filter using PYNQ. The performance of the designed accelerator is compared with its already available software implementation in the Numerical Python (NumPy) library and with published designs on FFT filter accelerators that used custom-designed Direct Memory Access (DMA) Intellectual Property (IP). However, customizing the IPs requires a lot of specialization in various areas, such as architecture, low-level programming, API development, etc. Therefore, in this research, we have used standard DMA IP available in Vivado along with run-time non-configurable (i.e. fixed size) FFT to show that one can still achieve a high speed-up, or even more and lesser hardware utilization (%) using smart design choices. The technique to employ that fixed size FFT design for different input sample sizes during run time is also explained in the paper. The results for delay, resources, and power consumption for different sample sizes are then shown and compared, which will aid in choosing the platform for computing FFT and designing such accelerators accordingly |
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