Abstract:
In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current ( I eff ) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and I eff are generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The I eff -models predict the oscillation frequency ( f OSC ) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- I eff -capacitance models account for the change in f OSC , tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular f OSC . Finally, the design methodology ensures that the desired f OSC is within the “linear” range of the VCO's-gain due to statistical variation of V th , V DD , etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.