MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques

Abstract

Due to small output swings and series stack transistors, Differential Ring Oscillators (DRO) and current starved ROs are not well suited for Near Threshold Voltage (NTV) regime. MOS varactor based Single Ended Ring Oscillators (SERO) is well suited in NTV regime as it gives full swing characteristics, wide tuning range and has very low power consumption. This paper proposes different architectures using MOS Varactor SERO (VBRO) that gives high oscillation frequency, wide tuning range, low area and power consumption without degrading the phase noise as compared to existing VCO topologies in NTV regime. The improvement in the tuning range of the VCO is because of the change in body capacitance of the DTMOS configuration used in the VBRO. The change in the center frequency with PVT variations is compared with that of an NTV DRO. Post layout simulations have been performed on parasitic extracted netlist using HSPICE in industrial 65nm CMOS Process Design Kit (PDK). Our VBRO architecture has tuning range of 0.425 - 2.13 GHz with phase noise of -95dBc/Hz at 0.6V supply. The power consumption is only 127μW and the Figure Of Merit (FOM) is 164.96dBc/Hz.