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Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies

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dc.contributor.author Mishra, Neeraj
dc.date.accessioned 2025-01-08T10:21:10Z
dc.date.available 2025-01-08T10:21:10Z
dc.date.issued 2015-06
dc.identifier.uri https://ieeexplore.ieee.org/abstract/document/7208062
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/16753
dc.description.abstract In stress enabled technologies the drive strength of multi-fingered (MF) transistors varies with the number of fingers (NF) because of Layout Dependent Effect (LDE). This is an important issue because MF transistors are widely used in integrated circuits. In this paper, we investigate performance variability issues in basic analog building blocks, such as current mirrors, common source amplifiers, and single ended differential amplifiers, designed using MF transistors. We observe that, due to the layout dependent channel mechanical stress, the analog performance parameters of these building blocks vary significantly. When the NF in MF transistors varies from one to seven, we observe that the copy current in cascode current mirrors vary by ~15%. For similar change in the NF there is ~22% and ~24% change in the bandwidth (BW) and the output resistance (R out ) respectively of an nMOS common source amplifier with pMOS current source load. We observe variations of ~32% in slew rate (SR), ~28% in BW, and ~12.4% in R out with the change in NF in a single ended differential amplifier. We model these variations as a function of NF in MF transistors since performance predictability in analog circuits is important. Finally, we designed a common source amplifier considering the impact of channel length on channel stress. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Common Source Amplifier en_US
dc.subject Current Mirror en_US
dc.subject Differential Amplifier en_US
dc.subject Multi-Fingered Transistor en_US
dc.subject Stress en_US
dc.title Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies en_US
dc.type Article en_US


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