Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory

Abstract

String read current (Iread) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated Iread with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness (TSi), using TCAD. We find that under a critical value of GS, Iread decreases with increase in TSi. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which Iread is independent of TSi, which is desirable to minimize the deviations in Iread arising from TSi variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that Iread increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm-2. The results presented in this paper are crucial for optimizing Iread and program/erase threshold voltage(VT) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance.