In this paper, we investigate the quality of MOSFET gate stacks where high- k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect ...

This paper demonstrates a 3D TCAD based approach towards the evaluation and pre-silicon development of nanoscale devices for advanced ESD protection concepts. Impact of various physical models and parameters on the accuracy ...

Cardiac problems are on the rise in the Indian sub-continent due to the changing life styles and food habits. Acute Myocardial Infraction (AMI) is becoming a major concern. In this paper, we report the development of ...

In this work, an aluminium-doped zinc oxide (AZO) thin film transistor, embedded in a polymer micro-cantilever, is demonstrated for nano-mechanical sensing applications. This device senses the surface stress due to a change ...

In this paper, we investigate the influence of forward and reverse body bias stress on the hot carrier induced degradation of MOS analog performance parameters. The underlying physical mechanisms are identified with the ...

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current ...

The variation in the threshold voltage caused by fluctuations in a device parameter is given by the product of a sensitivity coefficient and the fluctuation amount. In this paper, the sensitivity coefficient for each device ...

Hotwire CVD (HWCVD) deposited silicon rich nitride films were treated with O/sub 2/ plasma using RF plasma setup. The thickness of this oxynitride film was measured using spectroscopic ellipsometry. The film was treated ...

This letter analyzes the width dependence of gate current observed in nMOS transistors fabricated using the 28-nm gate-first CMOS process. It is experimentally shown that the gate current density is ~10× lower for 80-nm ...

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an ...