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Browsing BITS Faculty Publications by Author "Shekhar, Chandra"

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Admission Control Policy of Maintenance for Unreliable Server Machining System with Working Vacation

Shekhar, Chandra (Springer, 2017-03)

This investigation is concerned with the performance modeling of machining system operating under the admission control F-policy and server working vacation policy. The repair of failed machines is provided by an unreliable ...
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

Asati, Abhijit; Shekhar, Chandra (Springer, 2021-07)

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code ...
Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis

Asati, Abhijit; Shekhar, Chandra (IEEE, 2020)

Field-programmable gate arrays (FPGAs) have been used as pre-silicon validation platforms in VLSI designs. In this paper, we propose a FPGA-based you-only-look-once (YOLO) v2 object detector implementation that provides ...
Assessment of the Yoga on the Status of the Physical Fitness among Children of the Residential School

Shekhar, Chandra (IJLTEMAS, 2015-03)

In this article, we primarily study current health related physical fitness and health enhancing physical activity of residential school children of Birla Education Trust, Pilani, India. 276 school children, aged 8 to 14 ...
A brief review on retrial queue: Progress in 2010-2015

Shekhar, Chandra (IJASER, 2016-01)

The present survey is based on the principle of retrials in queueing theory i.e. the customers who repeatedly try to avail the services from the server, on finding dejection, because of the inactivity of the server to ...
Double orbit finite retrial queues with priority customers and service interruptions

Shekhar, Chandra (Elsevier, 2015-02)

The present study deals with the double orbit finite capacity retrial queues with unreliable server. The system facilitates the arrival of two types of customers known as priority and non priority customers and can hold a ...
Dual channel addition based FFT processor architecture for signal and image processing

Gupta, Anu; Shekhar, Chandra; Asati, Abhijit (ACM Digital Library, 2009-12)

This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey ...
Effect of thickness on the properties of ZnO thin films prepared by reactive RF sputtering

Gupta, Navneet; Kandpal, Kavindra; Shekhar, Chandra (Springer, 2018)

This work reports structural and electrical properties of ZnO thin film deposited by reactive RF sputtering at the room temperature, for thin film transistor (TFT) applications. To study the thickness dependent effect, ZnO ...
Estimation of scattering and intrinsic attenuation based on multiple lapse time window analysis in Sikkim Himalayan region, India

Shekhar, Chandra (Elsevier, 2018-11)

Attenuation of seismic wave energy was estimated in and around the source region of the Sikkim earthquake of 18 September, 2011 using aftershocks. The main shock had a moment magnitude 6.9 and after this main shock, ...
Fault-tolerant redundant repairable system with different failures and delays

Shekhar, Chandra (Emerald, 2020-04)

The internet of things and just-in-time are the embryonic model of innovation for the state-of-the-art design of the service system. This paper aims to develop a fault-tolerant machining system with active and standby ...
Finite Queueing Model with Multitask Servers and Blocking

Shekhar, Chandra (Scientific & Academic Publishing, 2012)

This paper deals with a Markovian queueing system having a multi-task service counters and finite queue in front of each counter. The total service of a customer is completed in three stages provided by two servers at three ...
Fuzzy analysis of machine repair problem with switching failure and reboot

Shekhar, Chandra (River Publication, 2014)

Multi-component machining systems are being used in every sphere of engineering sector such as job shops, flow lines, communication system, computer system, etc. This paper presents fuzzy analysis of availability characteristics ...
Genome wide analysis as Arabidopsis Thaliana reveals high frequency of AAAGN7CTTT motif

Shekhar, Chandra (Elsevier, 2014-12)

Sequence specific elements in DNA regulate transcription by recruiting transcription factors. The Dof proteins are a large family of transcription factors that share a single highly conserved zinc finger. The core to which ...
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance

Asati, Abhijit; Shekhar, Chandra (Academy Publisher, 2009-05)

The high-speed dynamic True Single Phase Clock (TSPC) logic design style offer fully pipelined logic circuits using only one clock signal, which makes clock distribution simple and compact. The conversion of simple logic ...
High-Level synthesis assisted design and verification framework for automotive radar processors

Asati, Abhijit; Shekhar, Chandra (Elsevier, 2020-10)

In radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the ...
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications

Asati, Abhijit; Shekhar, Chandra (Wiley, 2020-05)

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial ...
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic

Asati, Abhijit; Shekhar, Chandra (IEEE, 2008)

A high-speed radix-64 parallel multiplier using novel reduced delay partial product generator is proposed. The use of radix-64 Booth encoder and selector for partial product generation by Sang-Hoon (Sang-Hoon Lee et al., ...
A high-speed, hierarchical 16×16 array of array multiplier design

Asati, Abhijit; Shekhar, Chandra (IEEE, 2009)

Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for ...
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style

Asati, Abhijit; Shekhar, Chandra (IEEE, 2008)

The Array multipliers are generally preferred for smaller operand sizes due to their simpler VLSI implementations, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are ...
Load sharing redundant repairable systems with switching and reboot delay

Shekhar, Chandra (Elsevier, 2020-01)

Industry 4.0 depicts the fourth industrial revolution which prompts an insightful, associated and decentralized manufacturing. The prime viewpoint is an uninterrupted linkage between decision-makers, machines, and products ...

Now showing items 1-20 of 67

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