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Now showing items 1-10 of 11

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

Rao, V. Ramgopal (IEEE, 1999-07)
Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs

Rao, V. Ramgopal (IEEE, 1997-12)
The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations

Rao, V. Ramgopal (IEEE, 1997-10)
A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs

Rao, V. Ramgopal (Elsevier, 1999-05)
A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping

Rao, V. Ramgopal (Elsevier, 1999-09)
Application of charge pumping technique for sub-micron MOSFET characterization

Rao, V. Ramgopal (Elsevier, 1998-11)
Electric field tailoring in MBE-grown vertical sub-100 nm MOSFETs

Rao, V. Ramgopal (Elsevier, 1998-05)
Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

Rao, V. Ramgopal (IEEE, 1998-10)
100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

Rao, V. Ramgopal (IEEE, 1999)
Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics

Rao, V. Ramgopal (IEEE, 1999-09)

Now showing items 1-10 of 11