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Constant power consumption design of novel differential logic gate for immunity against differential power analysis
Gupta, Anu
(
IET
,
2018-11
)
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
(
Elsevier
,
2015
)
Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology
Gupta, Anu
(
Taylor & Francis
,
2015-04
)
CNTFET based design of content addressable memory cells
Gupta, Anu
(
IEEE
,
2013
)
Design of CNTFET-based 2-bit ternary ALU for nanoelectronics
Gupta, Anu
(
Taylor & Francis
,
2013-08
)
A Novel Design of Ternary Full Adder Using CNTFETs
Gupta, Anu
(
Springer
,
2014
)
An Operational Amplifier With Recycling Folded Cascode Topology And Adaptive Biaisng
Gupta, Anu
(
VLSICS
,
2014
)
A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region
Gupta, Anu
(
IJNIET
,
2013-02
)
Performance Evalution Of CNTFET-Based Sram Cell Design
Gupta, Anu
(
Inter Science
,
2012
)
Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Gupta, Anu
(
IJAEE
,
2012
)
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Author
Gupta, Anu (80)
Asati, Abhijit (21)
Shekhar, Chandra (10)
Chaturvedi, Nitin (5)
Gupta, Rajiv (5)
Asati, Abhijit (3)
Shenoy, Meetha V. (1)
Subject
EEE (80)
Iris localization (6)
Carbon nanotube field effect transistor (CNTFET) (4)
CMOS technology (4)
Logical effort (4)
Power-delay product (PDP) (4)
Architecture (3)
Carbon nanotube (CNT) field effect transistor (CNTFET) (3)
Carry ripple adder(CRA) (3)
Dedicated hardware architecture (3)
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Date Issued
2020 - 2024 (15)
2010 - 2019 (53)
2005 - 2009 (12)
Has File(s)
No (80)