Modelling of electrostatic discharge (ESD) protection circuits for CMOS ICS

dc.contributor.author	Gurunarayanan, S.
dc.date.accessioned	2021-09-03T14:43:28Z
dc.date.available	2021-09-03T14:43:28Z
dc.date.issued	2000-01-03
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/1904
dc.description	Supervisor: Dr. Chandra Shekhar	en_US
dc.language.iso	en	en_US
dc.publisher	BITS Pilani	en_US
dc.subject	Physics	en_US
dc.subject	Electrostatic Discharge (ESD)	en_US
dc.subject	Electrothermal Simulation	en_US
dc.title	Modelling of electrostatic discharge (ESD) protection circuits for CMOS ICS	en_US
dc.type	Thesis	en_US