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Browsing Department of Electrical and Electronics Engineering by Author "Chaturvedi, Nitin"

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Ab Initio Study of Carbon Nanotube Field Effect Transistor Gas Sensor for Detection of Ammonia and Nitrogen Dioxide Gas

Gupta, Navneet; Chaturvedi, Nitin (IEEE, 2022-07)

Lebel-free sensors are capable for sensing low concentration of gas molecules. In this article, the importance of Carbon Nanotube Field Effect Transistor (CNFET) is described for gas sensing application. The first principal ...
Adaptive Block Pinning Based: Dynamic Cache Partitioning for Multi-core Architectures

Chaturvedi, Nitin (IJCST, 2010-12)

This paper is aimed at exploring the various techniques currently used for partitioning last level (L2/L3)caches in multicore architectures, identifying their strengths and weaknesses and thereby proposing a novel partitioning ...
An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core Architectures

Chaturvedi, Nitin (IEEE, 2013)

With advent of new technologies there is exponential increase in multi-core processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with single, uniform ...
An adaptive coherence protocol with adaptive cache for multi-core architectures

Chaturvedi, Nitin (IEEE, 2013)

Next generation multicore processors and their applications will process massive amounts of data with significant sharing. Data movement between cores and shared cache hierarchy and its management impacts memory access ...
An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors

Chaturvedi, Nitin (Springer, 2015-07)

Most of today’s chip multiprocessors implement last-level shared caches as non-uniform cache architectures. A major problem faced by such multicore architectures is cache line placement, especially in scenarios where ...
Adaptive Zone-Aware Multi-bank on Chip last level L2 Cache Partitioning for Chip Multiprocessors

Chaturvedi, Nitin (IJCA, 2010)

This paper proposes a novel efficient Non-Uniform Cache Architecture (NUCA) scheme for the Last-Level Cache (LLC) to reduce the average on-chip access latency and improve core isolation in Chip Multiprocessors (CMP). The ...
A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications

Chaturvedi, Nitin (Springer, 2019)

Non-volatile SRAM (NV-SRAM) enables normally off computing while achieving faster power off/on time by storing the state in its locally embedded non-volatile elements. Emerging magnetic memory such as spin transfer torque ...
A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design

Chaturvedi, Nitin (IEEE, 2017)

With the advent of technology, a change from feature size to nanometer regime resulted in the scaling of operating voltages and dimensions. Reducing them can greatly boost the energy efficiency but it also leads to increased ...
Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET

Chaturvedi, Nitin (IEEE, 2017)

Using FinFET for designing of SRAM cells has shown a great deal of advantages over planar bulk devices due to the additional control on the gates and due to fully depleted behavior. The improvements have been noted in ...
Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation

Chaturvedi, Nitin (IEEE, 2020)

Over the past few decades, CMOS scaling has been a key driving factor to achieve faster, cheaper and denser digital systems. However, as the technology scales down, there is an exponential increase in leakage current which ...
Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications

Chaturvedi, Nitin (IEEE, 2021)

With the growth of big data applications such as voice/speech recognition, data mining, and computer vision, conventional computing system faces significant challenges. The increasing computational complexity and large ...
Design of a Robust Logic Gate using Magnetic Tunnel Junction

Chaturvedi, Nitin (IEEE, 2019)

In the era of big data, limited communication bandwidth poses a great challenge for the conventional Von-Neumann architecture. Moreover, significant data movement between memory and processor to handle ever growing data ...
Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications

Chaturvedi, Nitin (IEEE, 2022-08)

During the last few years, deep learning techniques are frequently applied in large-scale image processing, detection in a variety of computer vision, cognitive tasks, and information analysis applications. The execution ...
Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications

Chaturvedi, Nitin (World Scientific, 2021)

Most of today’s IoT-based computing systems offer an opportunity to build smarter systems for application areas such as healthcare monitoring and wireless sensor nodes. Since these systems are energy limited and remain ...
Design of non-volatile asynchronous circuit using CMOS-FDSOI/FinFET technologies

Chaturvedi, Nitin (IEEE, 2016)

This paper investigates the application of Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) in nonvolatile memory design. MTJs are favored in NVM design as they can provide indefinite data retention and very high ...
Development of micronutrients rich homemade extruded food products with theincorporation of processed foxtail millet, wheat and chickpea

Chaturvedi, Nitin (IJCH, 2014)

Food based approaches are recognized as an essential part of an urgently needed morecomprehensive strategy for improving nutrition by increasing the availability and consumption to combat iron andother micronutrient ...
A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications

Chaturvedi, Nitin (IEEE, 2021-04)

The emerging big data application poses many non-traditional challenges to a conventional computing system. The processing of a large amount of data in a conventional computing system involves frequent data movement between ...
An efficient adaptive block pinning for multicore architectures

Chaturvedi, Nitin (Elsevier, 2015-05)

Most of today’s multi-core processors feature last level shared L2 caches. A major problem faced by such multi-core architectures is cache contention, where multiple cores compete for usage of the single shared L2 cache. ...
An Efficient Data Access Policy in shared Last Level Cache

Chaturvedi, Nitin (World Scientific, 2015)

Future multi-core systems will execute massive memory intensive applications with significant data sharing. On chip memory latency further increases as more cores are added since diameter of most on chip networks increases ...
Energy-efficient data retention in D flip-flops using STT-MTJ

Chaturvedi, Nitin (Emerald, 2020-10)

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. ...

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