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Browsing Department of Electrical and Electronics Engineering by Subject "45 nm CMOS technology"

Now showing items 1-11 of 11

Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology

Vidhyadharan, Sanjay (Springer, 2019-02)

This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art ...
Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

Vidhyadharan, Sanjay (Taylor & Francis, 2023-01)

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less ...
Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node

Vidhyadharan, Sanjay (Springer, 2020-01)

In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ...
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger

Vidhyadharan, Sanjay (Elsevier, 2020-10)

This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than ...
Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs

Vidhyadharan, Sanjay (Taylor & Francis, 2021-04)

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented ...
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications

Vidhyadharan, Sanjay (IEEE, 2019)

For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that ...
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

Vidhyadharan, Sanjay (Elsevier, 2021-05)

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in ...
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder

Vidhyadharan, Sanjay (Taylor & Francis, 2020-03)

Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ...
TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node

Vidhyadharan, Sanjay (Springer, 2020-10)

Memristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics ...
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder

Vidhyadharan, Sanjay (Elsevier, 2021-01)

This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. ...
An ultra-low-power CNFET-based improved Schmitt triggerdesign for VLSI sensor applications

Vidhyadharan, Sanjay (Wiley, 2020-11)

To enable easy integration of Internet of Things (IoT) sensors with digital verylarge scale integrtaion (VLSI) circuits, the interface circuits need to operateefficiently even at low power supply voltages, consuming minimum ...

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Browsing Department of Electrical and Electronics Engineering by Subject "45 nm CMOS technology"

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