DSpace Home
→
BITS Faculty Publications
→
Department of Electrical and Electronics Engineering
→
Recent submissions

Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 1781-1800 of 2014

On-Chip Intelligent Frequency Scaling using Artificial Neural Networks

Gupta, Anu (IEEE, 2020)

Dynamic Voltage and Frequency Scaling (DVFS) is a popular method for reducing power consumption. Several DVFS techniques have been used for manually triggering a change in frequency to save power. This paper proposes a ...
Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate

Gupta, Anu (IEEE, 2019)

Differential Power analysis (DPA) method is frequently used for non-invasive side-channel attack to hack into the system. This paper proposes a novel DPA attack immune design of FinFET based logic gates which show dense ...
Power and Area Efficient Intelligent Hardware Design for Water Quality Applications

Gupta, Anu; Gupta, Rajiv (International Frequency Sensor Association, 2018-11)

The paper presents a power efficient and computationally less intensive intelligent hardware using artificial neural network for water quality applications. A compact Hardware Neural Network algorithm has been developed ...
Current-Mode PMOS capacitance multiplier

Gupta, Anu (IEEE, 2017)

This paper presents a novel technique to achieve an effective capacitance, multiples of up to 40 times that of a capacitor embedded in electronic circuits thus minimizing the area of silicon die. The technique employed for ...
Quad-NMOS cross-coupling for linearity enhancement in high frequency continuous-time OTA-C filters with IM3 below −70 dB

Gupta, Anu (IEEE, 2017)

This paper presents a technique to cancel nonlinearity in operational trans-conductance amplifiers for continuous-time high frequency (OTA)-C filters. The OTA's trans-conductance can be tuned from 40 to 177 μA/V, consuming ...
A hardware optimized low power RNM compensated three stage operational amplifier with embedded capacitance multiplier compensation

Gupta, Anu (IEEE, 2016)

This paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by ...
To predict the impact of passive architecture on the temperature conditions inside a building using ANN

Gupta, Anu; Gupta, Rajiv (IEEE, 2016)

The environmental impact of the building industry is significant. The construction industry constitutes a major part of the world's total energy consumption. As a result, building designers have constantly been urged to ...
Iris localization based on integro-differential operator for unconstrained infrared iris images

Gupta, Anu; Asati, Abhijit (IEEE, 2015)

Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained ...
Low power low noise bio-amplifier with adjustable gain for digital bio-signals acquisition systems

Gupta, Anu (IEEE, 2013)

This work describes a symmetrical power supplied (±1.8 V) 0.5 μm CMOS implementation of a bio-amplifier designed for use in digital acquisition systems. The whole acquisition system under fabrication will still contain a ...
Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime

Gupta, Anu; Asati, Abhijit (Inder Science, 2016)

Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of ...
Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime

Gupta, Anu; Asati, Abhijit (IEEE, 2015)

In this paper, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace [5] and Dadda [6] in sub-threshold regime. In order to reduce the hardware which ultimately ...
An Iris localization method for noisy infrared iris images

Gupta, Anu; Asati, Abhijit (IEEE, 2015)

Iris segmentation is an important step in iris biometrics and becomes more challenging when iris images are noisy. Iris segmentation process localizes iris in the iris image and detects eyelids also. The proposed method ...
Novel design of ternary magnitude comparator using CNTFETs

Gupta, Anu (IEEE, 2014)

This paper proposes a novel design of 1-bit ternary magnitude comparator (TMC) using carbon nano tube field effect transistors (CNTFETs). The proposed 1-bit TMC is designed for pass transistor logic style in order to achieve ...
A novel hardware efficient Digital Neural Network architecture implemented in 130nm technology

Gupta, Anu (IEEE, 2010)

Digital Neural Network implementations based on the perceptron model require the use of multi-bit representation of signals and weights. This results in the usage of multi-bit multipliers in each neuron, leading to ...
Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling

Gupta, Anu (COMSOL, 2013)

In high-speed digital design, strong electromagnetic coupling exists between adjacent transmission lines. This manifests itself in the form of crosstalk voltage induced on either line. Crosstalk is modeled in terms of ...
Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth

Gupta, Anu (IEEE, 2013)

A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical ...
A high gain, high CMRR two-stage fully differential amplifier using gm/Id technique for bio-medical applications

Gupta, Anu (IEEE, 2013)

This paper presents a well-defined method for the design of a high gain, high CMRR two-stage CMOS operational amplifier using 0.18μm CMOS technology for Bio-medical applications. The Op-amp consists of a cascade of ...
Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer

Gupta, Anu (IEEE, 2013)

The paper presents the implementation of a high speed energy efficient 4-bit binary CLA based incrementer decrementer. The design methodology is extensively based on static CMOS logic and transmission gate logic to achieve ...
Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime

Gupta, Anu; Asati, Abhijit (IEEE, 2014)

The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area ...
Performance evaluation of CNTFET based Dynamic Ternary Content Addressable Memory cell

Gupta, Anu (IEEE, 2013)

Carbon Nanotube Field-Effect Transistor (CNTFET) with high mobility due to ballistic transport operation and low OFF current capability has proved to be a promising alternate to the conventional CMOS technology. This paper ...

Now showing items 1781-1800 of 2014

Search DSpace

Advanced Search

Browse

All of DSpace
This Collection
- By Issue Date
- Authors
- Titles
- Subjects

Recently added

Department of Electrical and Electronics Engineering: Recent submissions

Search DSpace

Browse

All of DSpace

This Collection

My Account