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Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 201-220 of 1605

Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs

Rao, V. Ramgopal (IEEE, 2001-04)

Metal–nitride–semiconductor FETs (MNSFETs) having channel lengths down to 100 nm and a novel jet vapor deposited (JVD) Si3N4 gate dielectric have been fabricated and characterized. When compared with MOSFETs having a ...
Status and Trends in Molecular Electronics

Rao, V. Ramgopal (Taylor & Francis, 2002)

Miniaturization of integrated circuits is happening at a rapid pace since the last two decades. Physical limits are beginning to saturate the growth of Si-CMOS technology and have prompted technologists to look for alternative ...
The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

Rao, V. Ramgopal (IEEE, 2002-05)

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte ...
Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Rao, V. Ramgopal (IEEE, 2002-06)

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V/sub T/ ...
Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique

Rao, V. Ramgopal (IEEE, 2001-07)

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current ...
Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique

Rao, V. Ramgopal (IEEE, 2001-07)

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current ...
Ultra-thin silicon nitride by hot wire chemical vapor deposition (HWCVD) for deep sub-micron CMOS technologies

Rao, V. Ramgopal (Elsevier, 2002-07)

Silicon nitride is considered a promising candidate to replace thermal oxide dielectrics, as the latter is reaching its scaling limits due to the excessive increase in the gate tunneling leakage current. The novel hot wire ...
Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Rao, V. Ramgopal (IEEE, 2003-12)

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for ...
CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

Rao, V. Ramgopal (IEEE, 2003-10)

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable ...
Nitrogen dilution effects on structural and electrical properties of hot-wire-deposited a-SiN:H films for deep-sub-micron CMOS technologies

Rao, V. Ramgopal (Elsevier, 2003-04)

Hot-wire chemical vapor-deposited silicon nitride is a potential dielectric material compared to glow-discharge-deposited material due to its lower hydrogen content. In several earlier publications we have demonstrated ...
A new method to characterize border traps in submicron transistors using hysteresis in the drain current

Rao, V. Ramgopal (IEEE, 2003-04)

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border ...
Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

Rao, V. Ramgopal (IEEE, 2003-04)

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models ...
Highly conducting doped poly-Si deposited by hot wire CVD and its applicability as gate material for CMOS devices

Rao, V. Ramgopal (Elsevier, 2003-04)

Highly conducting p- and n-type poly-Si:H films were deposited by hot wire chemical vapor deposition (HWCVD) using SiH4+H2+B2H6 and SiH4+H2+PH3 gas mixtures, respectively. Conductivity of 1.2×102 (Ω cm)−1 for the p-type ...
Device and circuit performance issues with deeply scaled high-K MOS transistors

Rao, V. Ramgopal (Institute of Electronics Engineers of Korea, 2003)

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high- K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric ...
Reliability of ultrathin JVD silicon nitride MNSFETs under high field stressing

Rao, V. Ramgopal (IEEE, 2003-08)

In this paper, we study the reliability of n-channel Metal-Nitride-Silicon FETs fabricated using ultrathin Jet Vapor Deposited (JVD) Silicon Nitride gate dielectric under constant voltage stressing. Due to the stress, ...
Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations

Rao, V. Ramgopal (IEEE, 2004-06)

The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We ...
The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

Rao, V. Ramgopal (IEEE, 2004-09)

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral ...
Deep sub-micron device and analog circuit parameter sensitivity to process variations with halo doping and its effect on circult linearity

Rao, V. Ramgopal (Institute of Pure and Applied Physics, 2005)

Single halo (SH) and double halo (DH) metal oxide semiconductor field effect transistors (MOSFETs) have been reported to exhibit excellent short channel performance in the sub 100 nm regime. In this work, the effect of ...
Optimum Body Bias Constraints for Leakage Reduction in High-k Complementary Metal–Oxide–Semiconductor Circuits

Rao, V. Ramgopal (IOP, 2009)

A significantly increased subthreshold leakage is observed in devices with high-k gate dielectric due to gate fringing field effects. Further, the drain to body band-to-band tunnelling leakage (BTBT) current also increases ...
Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

Rao, V. Ramgopal (IEEE, 2005-03)

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure ...

Now showing items 201-220 of 1605

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