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Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 41-60 of 1605

Design and analysis of wearable patch antenna array for MBAN applications

Rano, Dinesh (IEEE, 2016)

Design idea of wearable rectangular patch antenna and its array for MBAN (2.36 - 2.4 GHz) applications are proposed in this paper. Microstrip line with quarter wave transformer is used for feeding purpose. Polyamide lossy ...
Extremely compact EBG-backed antenna for smartwatch applications in medical body area network

Rano, Dinesh (IET, 2019-03)

This paper presents design of a compact interdigital electromagnetic band gap unit cell (IDE) for wearable applications in the medical body area network (MBAN) band. The uniqueness of the proposed cell is in its ability ...
Radiation Induced Interface State Generation in Nitrided and Reoxidized Nitrided Gate Oxides

Rao, V. Ramgopal (AIP, 1992-01)

Reoxidized nitrided oxide is compared with nitrided oxides and dry SiO2 for radiation‐induced interface‐state generation (ΔDitm) and midgap voltage shifts (ΔVmg). The suppression of ΔDitm observed with heavy nitridation ...
Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs

Rao, V. Ramgopal (IEEE, 1997-12)

In this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, ...
The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations

Rao, V. Ramgopal (IEEE, 1997-10)

Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel ...
Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

Rao, V. Ramgopal (IEEE, 1998-10)

SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices ...
A Study of the Effect of Plasma Etch Damage on Sub-Micron MOSFET's Flicker Noise Properties

Rao, V. Ramgopal (IEEE, 1998-09)
Plasma process induced abnormal 1/f noise behavior in deep sub-micron MOSFETs

Rao, V. Ramgopal (IEEE, 1998)

The effect of plasma damage on the MOSFET's flicker noise properties is examined in this work. We observe an abnormal noise peak in the 1/f noise spectrum at around 2 kHz which is a characteristic of the plasma damage. The ...
Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics

Rao, V. Ramgopal (IEEE, 1999-09)

High-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to ...
Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique

Rao, V. Ramgopal (IEEE, 1999)

Metal-Nitride-Semiconductor f"'En:" with channel lengths down to 100 nm and a novel .leI Vapor f)eposited (JVD) SiN gate dielectric are fabricated and characterized for their hot-carrier reliability. A novel charge ...
Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS

Rao, V. Ramgopal (IEEE, 1999)

The effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher I/sub dsat/ and g/sub msat/, lower I/sub off/, and superior ...
100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

Rao, V. Ramgopal (IEEE, 1999)

Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By ...
Low temperature Hot-Wire CVD nitrides for deep sub-micron CMOS technologies

Rao, V. Ramgopal (The International Society for Optical Engineering, 2000)

In this work we report results on MNS capacitors with the silicon nitride films fabricated by using a novel Hot-Wire CVD technique. The dependence of deposition parameters on the film properties is looked into. Our electrical ...
Reliability studies on sub 100 nm SOI-MNSFETs

Rao, V. Ramgopal (IEEE, 2000)

SOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si/sub 3/N/sub 4/) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in ...
Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs

Rao, V. Ramgopal (The Japan Society of Applied Physics, 2001)

(Vp) well below the bandgap voltage of silicon has received widespread attention [1,2,3]. Substrate currents (Isue) for drain voltages down to 0.6V [1] and floating body effects in SOI devices down to 0.8V [2] were ...
Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime

Rao, V. Ramgopal (IEEE, 2000-09)

Drain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron ...
Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs

Rao, V. Ramgopal (Elsevier, 2001-07)

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where ...
Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics

Rao, V. Ramgopal (IEEE, 2001)

In this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel ...
Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering

Rao, V. Ramgopal (IEEE, 2001)

A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that ...
Reliability issues of ultra thin silicon nitride (a-SiN:H) by hot wire CVD for deep sub-micron CMOS technologies

Rao, V. Ramgopal (SPIE, 2001)

The reliability of gate dielectric is of high importance, especially as its thickness is reaching atomic dimensions. The gate leakage currents and the operating fields can be very high in devices with these ultra thin gate ...

Now showing items 41-60 of 1605

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