DSpace Home
→
BITS Faculty Publications
→
Department of Electrical and Electronics Engineering
→
Recent submissions

Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 461-480 of 1659

Photoresponse of an off-stoichiometry thiol–ene–epoxy (OSTE+) polymer

Rao, V. Ramgopal (RSC, 2022)

The development of an off-stoichiometry thiol–ene–epoxy (OSTE+) based functional polymer has paramount importance for smart photonic sensor integrated lab-on-chip device applications. A modest attempt has been made to ...
Detection of tomato leaf curl New Delhi virus DNA using U-bent optical fiber-based LSPR probes

Rao, V. Ramgopal (Elsevier, 2022-12)

The detection of Tomato leaf curl New Delhi virus (ToLCNDV) DNA has been presented using U-bent fiber optic sensor (FOS) by an evanescent wave absorption method in the visible region. The localized surface plasmon resonance ...
Gate voltage tunable temperature coefficient of resistance of WSe2 for thermal sensing applications

Rao, V. Ramgopal (IEEE, 2022-05)

Two-dimensional (2D) materials have layered structure with unique properties. One of the properties of interest is the temperature coefficient of resistance (TCR) which should be large for fast thermal sensors. The TCR is ...
Understanding the Microscopic Origin of the Contact Resistance at the Polymer–Electrode Interface

Rao, V. Ramgopal (ACS, 2023-10)

Contact resistance (RC) in organic devices originates from a mismatch in energy levels between injecting electrodes and organic semiconductors (OSCs). However, the microscopic effects governing charge transfer between ...
Emerging synthesis and characterization techniques for hybrid polymer nanocomposites

Rao, V. Ramgopal (IOP, 2023-10-17)

Metallic nanoparticles and carbon nanotubes are two of the most promising nanomaterials, due to their distinctive properties occurring from spatial confinement of electron–hole pairs. The unique combination of metallic ...
Comments on An Efficient Method based on Self-Generating Disjoint Minimal Cut-Sets for Evaluating Reliability Measures of Interconnection Networks

Chakraborty, Suparna (Totem Publisher, 2014)

The recent paper published in IJPE by Tripathy et al. [1] presented a new method based on self-generating, non-redundant and disjoint cutsets to evaluate the three important reliability measures, viz., two-terminal, ...
Subset Cut Enumeration of Flow Networks with Imperfect Nodes

Chakraborty, Suparna (Totem Publisher, 2014)

A general assumption made in evaluation of flow network reliability is perfectly reliable nodes. Under such assumption, network reliability is evaluated through subset cut or composite path set approaches. This paper ...
Irredundant Subset Cut Enumeration for Reliability Evaluation of Flow Networks

Chakraborty, Suparna (IEEE, 2015-12)

Capacity Related Reliability (CRR) is an important performance index for flow networks. Most of the CRR evaluation techniques proposed in literature, which deal with subset cut enumeration from minimal cut sets, generate ...
On Area Coverage Reliability of Mobile Wireless Sensor Networks With Multistate Nodes

Chakraborty, Suparna (IEEE, 2020-05)

Wireless sensor networks (WSNs) are a special type of infrastructure-less network made up of a large number of tiny sensor nodes with limited energy, processing, and communication capabilities. WSNs have applications in ...
A Monte-Carlo Markov chain approach for coverage-area reliability of mobile wireless sensor networks with multistate nodes

Chakraborty, Suparna (Elsevier, 2020-01)

A mobile Wireless Sensor Network (mWSN) is composed of a large number of tiny, inexpensive resource-constrained sensors scattered in the field of interest, with the sink node or the data collector moving around the field. ...
Minimal Path-Based Reliability Model for Wireless Sensor Networks With Multistate Nodes

Chakraborty, Suparna (IEEE, 2020-03)

Wireless sensor networks (WSNs) find application in various fields like environmental monitoring, health-care, land security, and many more. To ease our day-to-day activity, WSNs have become an integral tool for complex ...
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications

Vidhyadharan, Sanjay (IEEE, 2019)

For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that ...
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices

Vidhyadharan, Sanjay (IEEE, 2019)

Recent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology ...
Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology

Vidhyadharan, Sanjay (Springer, 2019-02)

This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art ...
Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology

Vidhyadharan, Sanjay (Springer, 2019-02)

In this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS ...
A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

Vidhyadharan, Sanjay (Springer, 2019-06)

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current Ion, while the off current Ioff remains an order lower than the analogous ...
An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

Vidhyadharan, Sanjay (Springer, 2019-11)

Adiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic ...
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder

Vidhyadharan, Sanjay (Taylor & Francis, 2020-03)

Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ...
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

Vidhyadharan, Sanjay (Elsevier, 2020-07)

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while ...
Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node

Vidhyadharan, Sanjay (Springer, 2020-01)

In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ...

Now showing items 461-480 of 1659

Search DSpace

Advanced Search

Browse

All of DSpace
This Collection
- By Issue Date
- Authors
- Titles
- Subjects

Recently added

Department of Electrical and Electronics Engineering: Recent submissions

Search DSpace

Browse

All of DSpace

This Collection

My Account