MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. ...

In this paper we systematically investigate the effects of the varying tilt angle of the halo implants on the different device performance parameters of 100 nm lateral asymmetric channel (LAC) MOSFETs. The tilt angle is ...

In sub-1V CNIOS technologies, the approach of increasing speed and reducing area of circuits with scaling is facing a severe challenge due to exponential increase in leakage currents. The DTMOS device has an ideal subthreshold ...

It is shown that body doping can be used to match the Bulk FinFETs' DC performance with that of SOI FinFETs, even down to 22 nm technology node, by using calibrated full 3D device simulations. However higher body doping ...

In order to achieve patterned surfaces for microfluidic applications, we show for the first time the use of self-assembled monolayer (SAM) of Hydroxy-phenyl porphyrin on SiO 2 surface following a chemical procedure. The ...

In this paper we present a completely closed-form inversion charge-based model for the drain current and conductance of a symmetric double-gate MOSFET based on the drift-diffusion transport mechanism, that takes into account ...

In this paper we have studied the application of metallated porphyrin self assembled monolayers (SAMs) as Cu diffusion barriers for ultra-large scale integration (ULSI) CMOS applications. The results for Cu/SiO 2 /Si and ...

Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T FIN ) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology ...

This work establishes a novel circuit simulation methodology for organic thin film transistors (OTFTs). Because of a lack of well developed physical models for OTFTs and due to the limitations of conventional parameter ...

In this paper, we have studied the application of metallated porphyrin self-assembled monolayer (SAM) as a copper diffusion barrier for low-k inter-metal dielectric (IMD) CMOS technologies. SAM formed on hydrogen silesquioxane ...