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Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 521-540 of 1936

Low temperature-high pressure grown thin gate dielectrics for MOS applications

Rao, V. Ramgopal (Elsevier, 1999-09)

In this study we propose high pressure grown oxide (HIPOX) as an alternative low-temperature MOS gate insulator and show that it performs excellently in comparison to other widely reported low-temperature deposited oxides. ...
A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs

Rao, V. Ramgopal (Elsevier, 1999-05)

A new charge pumping (CP) technique is proposed to obtain the spatial profile of interface-state density (Nit) and oxide charges (Not) near the drain junction of hot-carrier stressed MOSFETs. Complete separation of Nit ...
Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs

Rao, V. Ramgopal (IOP, 1999)

Scaling of metal-oxide-semiconductor (MOS) transistors to smaller dimensions has been a key driving force in the IC industry. As we approach the sub-quarter micron regime, a whole new set of problems regarding the device ...
The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

Rao, V. Ramgopal (IEEE, 1999-07)

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum ...
Exploration of Velocity Overshoot in a High-Performance Deep Sub-0.1- m SOI MOSFET with Asymmetric Channel Profile

Rao, V. Ramgopal (IEEE, 1999-10)

The electron velocity overshoot phenomenon in the inversion layer is experimentally investigated using a novel thinfilm silicon-on-insulator (SOI) test structure with channel lengths down to 0.08 m. The uniformity of ...
Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Rao, V. Ramgopal (IEEE, 2000-04)

The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The ...
A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

Rao, V. Ramgopal (IEEE, 2000-01)

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N/sub it/) and oxide (N/sub 0t/) traps in hot-carrier stressed MOSFETs. Direct ...
Comparison of Sub-Bandgap Impact Ionization in Sub-100 nm Conventional and Lateral Asymmetrical Channel nMOSFETs

Rao, V. Ramgopal (IOP, 2001)

Sub-bandgap impact ionization is compared in 100 nm channel length conventional channel and laterally asymmetrical n-channel metal oxide semiconductor field effect transistor (MOSFET). An abnormal increase of the gate ...
A simple and direct technique for interface characterization of SOI MOSFETs and its application in hot carrier degradation studies in sub-100 nm JVD MNSFETs

Rao, V. Ramgopal (Elsevier, 2001-11)

Conventional interface characterization techniques, such as charge pumping, cannot be applied to SOI devices due to lack of a substrate contact in these devices. A lock-in-amplifier based multi-frequency transconductance ...
Low temperature silicon nitride deposited by Cat-CVD for deep sub-micron metal–oxide–semiconductor devices

Rao, V. Ramgopal (Elsevier, 2001-09)

Silicon nitride as a gate dielectric can improve the performance of ULSI CMOS devices by decreasing the gate leakage currents. In this paper we report a a-SiN:H gate dielectric fabricated using Cat-CVD at a relatively low ...
Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI–MOSFETs

Rao, V. Ramgopal (Elsevier, 2001-07)

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where ...
Sub-100 nm CMOS circuit performance with high-K gate dielectrics

Rao, V. Ramgopal (Elsevier, 2001-07)

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly ...
A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique

Rao, V. Ramgopal (Elsevier, 2001-10)

The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determined using a novel charge pumping technique. Detailed post-stress interface ...
Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs

Rao, V. Ramgopal (IEEE, 2001-04)

Metal–nitride–semiconductor FETs (MNSFETs) having channel lengths down to 100 nm and a novel jet vapor deposited (JVD) Si3N4 gate dielectric have been fabricated and characterized. When compared with MOSFETs having a ...
Status and Trends in Molecular Electronics

Rao, V. Ramgopal (Taylor & Francis, 2002)

Miniaturization of integrated circuits is happening at a rapid pace since the last two decades. Physical limits are beginning to saturate the growth of Si-CMOS technology and have prompted technologists to look for alternative ...
The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

Rao, V. Ramgopal (IEEE, 2002-05)

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte ...
Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Rao, V. Ramgopal (IEEE, 2002-06)

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V/sub T/ ...
Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique

Rao, V. Ramgopal (IEEE, 2001-07)

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current ...
Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique

Rao, V. Ramgopal (IEEE, 2001-07)

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current ...
Ultra-thin silicon nitride by hot wire chemical vapor deposition (HWCVD) for deep sub-micron CMOS technologies

Rao, V. Ramgopal (Elsevier, 2002-07)

Silicon nitride is considered a promising candidate to replace thermal oxide dielectrics, as the latter is reaching its scaling limits due to the excessive increase in the gate tunneling leakage current. The novel hot wire ...

Now showing items 521-540 of 1936

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