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Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 61-80 of 1605

Study of Degradation in Channel Initiated Secondary Electron Injection Regime

Rao, V. Ramgopal (IEEE, 2001-09)

This paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current ...
The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance

Rao, V. Ramgopal (IEEE, 2001-09)

The potential impact of high permittivity gate dielectrics on the circuit performance is studied over a wide range of gate dielectrics using 2-Dimensional device and monte-carlo simulations. It is found that there is ...
High Field Stressing Effects in JVD Nitride Capacitors

Rao, V. Ramgopal (SPIE, 2001)

The performance of Jet Vapour Deposited (JVD) Silicon Nitride devices under high field stressing is reported in this paper. Border traps were generated when n-substrate capacitors were stressed with negative gate voltages. ...
Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs

Rao, V. Ramgopal (IEEE, 2001-10)

This paper presents results on the characterization of Lateral Asymmetric Channel (LAC) thin film silicon-on-insulator (SOI) MOSFETs. These devices are compared with conventional SOI MOSFETs having uniform channel doping. ...
Simulation Study of Non-Quasi Static Behaviour of MOS Transistors

Rao, V. Ramgopal (TechConnect, 2002-04)

In this paper, we study the “non-quasi static” (NQS) behaviour of MOS transistors using an exact quasi static Look-up Table (LUT) [1] MOSFET model implemented in a general-purpose circuit simulator SEQUEL [2], device ...
Nitrogen dilution effects on structural and electrical properties of hot-wire-deposited a-SiN:H films for deep-sub-micron CMOS technologies

Rao, V. Ramgopal (Elsevier, 2003-04)

Hot-wire chemical vapor-deposited silicon nitride is a potential dielectric material compared to glow-discharge-deposited material due to its lower hydrogen content. In several earlier publications we have demonstrated ...
Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability

Rao, V. Ramgopal (IEEE, 2002-09)

Single halo (SH) MOSFETs are recently proposed for mixed signal applications in view of their superior analog performance such as gain, transconductance, output resistance etc [1]. In this work, we investigate the hot ...
Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs

Rao, V. Ramgopal (IEEE, 2002-07)

An experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric ...
Suppression of boron penetration by hot wire CVD polysilicon

Rao, V. Ramgopal (IEEE, 2002)

In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to ...
Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

Rao, V. Ramgopal (Springer, 2011-02)

We have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. ...
Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors

Rao, V. Ramgopal (Springer, 2011-02)

This paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier ...
Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET

Rao, V. Ramgopal (Springer, 2011-02)

In this paper we discuss a new method for measuring border trap density (Nbt) in sub-micron transistors using the hysteresis in drain current. We have used this method to measure Nbt in jet Vapour Deposited (JVD) Silcon ...
Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs

Rao, V. Ramgopal (Springer, 2011)

It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept ...
Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

Rao, V. Ramgopal (Springer, 2011-02)

The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance ...
Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETs

Rao, V. Ramgopal (Springer, 2001)

A study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction ...
Thin film single halo (SH) SOI nMOSFETs - hot carrier reliability for mixed mode applications

Rao, V. Ramgopal (IEEE, 2003)

For the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for mixed signal applications. The single halo structure has a high pocket ...
The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs

Rao, V. Ramgopal (IEEE, 2003-09)

The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements ...
Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs

Rao, V. Ramgopal (IEEE, 2003)

The effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (V/sub CG/) and is insensitive to changes in ...
Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications

Rao, V. Ramgopal (IEEE, 2003-01)

In this paper, we report a study on the small signal characterization and simulation of single halo (SH) thin film silicon-on-insulators (SOI) nMOSFETs for analog and mixed signal applications. The single halo structure ...
Application of look-up table approach to high-K gate dielectric MOS transistor circuits

Rao, V. Ramgopal (IEEE, 2003-01)

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an ...

Now showing items 61-80 of 1605

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