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Department of Electrical and Electronics Engineering: Recent submissions

Now showing items 81-100 of 1605

Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

Rao, V. Ramgopal (IEEE, 2003-01)

This paper analyzes in detail the fringing induced barrier lowering (FIBL) in MOS transistors with high-k gate dielectrics using 2D device simulations. We found that the device short channel performance is degraded with ...
A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime

Rao, V. Ramgopal (IEEE, 2003-02)

The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS scaling into the sub-100 nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately ...
The influence of process variations on the Halo MOSFETs and its implications on the analog circuit performance

Rao, V. Ramgopal (IEEE, 2004)

Lateral Asymmetric Channel (LAC) and Double Halo (DH) MOSFETs have been reported to exhibit excellent properties for mixed signal CMOS applications. In this work, the effect of process variations such as gate oxide thickness, ...
Understanding the NBTI Degradation in Halo- Doped Channel p-MOSFETs

Rao, V. Ramgopal (IEEE, 2004-07)

The role of initial interface damage for negative bias temperature instability (NBTI) degradation has been examined for short channel MOSFET devices. In this paper we present a detailed study of the role of initial ...
Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS Memories

Rao, V. Ramgopal (IEEE, 2004-07)

This paper discusses the effect of localized charge storage on sub-threshold swing and threshold voltage in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cells. By analyzing the change in potential contours, ...
Effectiveness of Optimum Body Bias for Leakage Reduction in High-K CMOS Circuits

Rao, V. Ramgopal (SSDM, 2004)

Optimal body bias (OBB) has been recently shown to be effective in minimizing the exponentially increasing drain leakage in deep submicron technologies [1], [2]. High permittivity (high K) gate dielectrics, proposed to ...
Understanding the Impact of Process Variations on Analog Circuit Performance with Halo Channel Doped Deep Sub-Micron CMOS Technologies

Rao, V. Ramgopal (SSDM, 2004)

Single Halo (SH) and Double Halo (DH) MOSFETs are reported to suppress short channel effects in the sub 100nm regime [1]-[2]. Also, it has recently been shown that SH technologies exhibit good analog performance ...
Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films

Rao, V. Ramgopal (IEEE, 2004-12)

Hotwire CVD (HWCVD) deposited silicon rich nitride films were treated with O/sub 2/ plasma using RF plasma setup. The thickness of this oxynitride film was measured using spectroscopic ellipsometry. The film was treated ...
A new drain voltage enhanced NBTI degradation mechanism [pMOSFETs]

Rao, V. Ramgopal (IEEE, 2005)

Interface state generation and threshold voltage degradation for various channel length devices, stressed at different drain bias conditions, has been studied. It is found that the NBTI (negative bias temperature instability) ...
A meso-pyridyl porphyrin self-assembled monolayer on gold substrates for molecular electronics applications

Rao, V. Ramgopal (IEEE, 2005-07)

In this paper, we report the formation of meso-pyridyl porphyrin self assembled monolayers on a gold substrate, its surface topography by AFM and its electrical characteristics by STS. The self-assembly was accomplished ...
Forward Body-biased Single Halo MOS Devices for Low Voltage Analog Circuits

Rao, V. Ramgopal (IEEE, 2005)

Forward body bias has been shown to be an effective way to improve the digital performance of CMOS circuits. However, as the technologies scale into the sub 100 nm regime, body bias sensitivity degrades, making the application ...
Performance of Channel Engineered SDODEL MOSFET for Mixed Signal Applications

Rao, V. Ramgopal (IEEE, 2005)

In this paper, with the help of simulations the concepts of source/drain (S/D) impurity profile engineering are proposed for reduction of the junction capacitance (Cj). It has been recently shown that it is possible to ...
Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies

Rao, V. Ramgopal (IEEE, 2006)

MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. ...
Analog Device and Circuit Performance Degradation under Substrate Enhanced Hot Carrier Stress Conditions

Rao, V. Ramgopal (IEEE, 2006)

In this paper, we investigate the influence of forward and reverse body bias stress on the hot carrier induced degradation of MOS analog performance parameters. The underlying physical mechanisms are identified with the ...
The Effects of Varying Tilt Angle of Halo Implant on the Performance of Sub 100nm LAC MOSFETs

Rao, V. Ramgopal (IEEE, 2006-08)

In this paper we systematically investigate the effects of the varying tilt angle of the halo implants on the different device performance parameters of 100 nm lateral asymmetric channel (LAC) MOSFETs. The tilt angle is ...
Pentacene Organic Field Effect Transistors on Flexible substrates with polymer dielectrics

Rao, V. Ramgopal (IEEE, 2007)

Pentacene organic field effect transistors are fabricated using polymethyl methacrylate (PMMA) as a gate dielectric on flexible polymeric substrates like the indium tin oxide coated polyethylene terephthalate (ITO coated ...
Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics

Rao, V. Ramgopal (IEEE, 2007)

In sub-1V CNIOS technologies, the approach of increasing speed and reducing area of circuits with scaling is facing a severe challenge due to exponential increase in leakage currents. The DTMOS device has an ideal subthreshold ...
Parasitic Effects Depending on Shape of Spacer Region on FinFETs

Rao, V. Ramgopal (IOP, 2007)

Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the ...
Improving the DC performance of Bulk FinFETs by Optimum Body Doping

Rao, V. Ramgopal (IEEE, 2007)

It is shown that body doping can be used to match the Bulk FinFETs' DC performance with that of SOI FinFETs, even down to 22 nm technology node, by using calibrated full 3D device simulations. However higher body doping ...
A Simple and Direct Method for Interface Characterization of OFETs

Rao, V. Ramgopal (IEEE, 2007)

Multi-frequency transconductance technique is successfully applied in this work for the first time for interface characterization of OFETs. Standard charge pumping measurements are used on silicon MOSFETs for the validation ...

Now showing items 81-100 of 1605

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