Abstract:
Carbon nanotube field effect transistor (CNTFET) shows great promises as extension to Silicon MOSFET for building high performance and low power VLSI circuit. Three-valued (ternary) logic is a promising alternative to traditional binary logic for accomplishing simplicity and energy efficiency in modern digital design. Ternary logic has an elegant association with CNTFET because the best way to design ternary circuit is the multiple-threshold method and desired threshold voltage can be easily achieved by utilizing different diameter of CNT in CNTFET device. newlineThis thesis develops designs of ternary arithmetic and logic unit (TALU) and content addressable memory cell using CNTFETs. First, 2-bit hardware optimized ternary ALU (HO-TALU) is presented. 2-bit HO-TALU gets minimization in required hardware at both architectural as well as at circuit level. At architecture level, HO-TALU has a new adder-subtractor (AS) module which performs both addition and subtraction operations using an adder module only with the help of multiplexers. Thus, it eliminates a subtractor module from the conventional architecture. At circuit level, HO-TALU minimizes ternary function expressions and utilizes binary gates along with ternary gates in realization of functional modules: AS, multiplier, comparator and exclusive-OR. AS module has a minor loss in power-delay product (PDP) but multiplier, comparator and exclusive-OR modules show improved PDP. As a consequence, HO-TALU gets significant reduction in device count with marginally increase in PDP for addition and subtraction operations only in comparison with CNTFET-based ternary designs available in the literature. Design of 2-bit HO-TALU is modified to develop a 2-bit HO-TALU slice which could be easily cascaded to construct N-bit HO-TALU. newlineTernary full adder (TFA) which is a basic sub-block of AS module, is modified using different circuit techniques to improve its efficiency in terms of PDP. Three new designs of TFA are presented.
