Abstract:
The objective of this thesis is to explore the design space of two specific data path newlineelements (viz multipliers and barrel shifters) of different bit width at architectural-level, newlineat logic design level, and at transistor size level to select proper architecture, logic design newlinestyle and physical device sizes; keeping in a view their effects on performance (circuit newlinedelay), average power consumption and core area. newlineThe multipliers and barrel shifters are the fundamental data path elements required in newlinehigh performance Standard Digital Signal Processors and ASIC Digital Signal newlineProcessors used for digital signal processing (DSP). Different multiplier and barrel newlineshifter architectures show trade-offs between propagation delay, average power newlineconsumption and transistor counts. In deep sub-micron technologies, the simple gatelevel newlineanalyses are inadequate to validate particular data path architectures. In this thesis newlinewe considered the effects of wiring parasitics and MOS parasitics in the assessment of newlinearchitecture. The selected word widths for different multiplier and barrel shifter newlinearchitectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications. newlineA schematic and physical library consisting of functional cells was defined for static newlineCMOS logic design style, transmission gate (TG) logic design styles, dual rail domino newlinelogic design style and true single phase clock (TSPC) logic design style. Versions of the newlinephysical libraries were developed using three different sizes of transistors. The layout assemblies for the 4-bit, 8-bit, 12-bit and 16-bit multiplier and barrel shifter circuits were carried out using these cell libraries using automatic place and route tool LEDIT (SPR) newlinefrom M/s Tanner Research Inc. The circuit delay and average power dissipation then newlineanalyzed for each implementation of the multiplier and barrel shifter circuit using the same logic design style but utilizing three different physical libraries differing in their transistor sizes as described above.
