High Performance Binary Logarithmic and BCD Multiplier Architectures

dc.contributor.author	Ahmed, Syed Ershad
dc.date.accessioned	2022-09-29T11:43:23Z
dc.date.available	2022-09-29T11:43:23Z
dc.date.issued	2017
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/5179
dc.description	Under Supervision: Srinivas, M. B	en_US
dc.language.iso	en	en_US
dc.publisher	BITS Pilani	en_US
dc.subject	Electrical & Electronics Engineering	en_US
dc.subject	Technology	en_US
dc.title	High Performance Binary Logarithmic and BCD Multiplier Architectures	en_US
dc.type	Thesis	en_US