| dc.contributor.author |
Naidu, S.R. |
|
| dc.date.accessioned |
2023-01-24T10:12:41Z |
|
| dc.date.available |
2023-01-24T10:12:41Z |
|
| dc.date.issued |
2007 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/4092056/keywords#keywords |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8696 |
|
| dc.description.abstract |
This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in isolation or they could be used together. Both techniques can be readily implemented in any statistical timing framework. We compare our proposed Monte-Carlo simulation with traditional Monte-Carlo simulation in a rigorous framework and show that the new method is up to 2 times as efficient as the traditional method |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
Computer Science |
en_US |
| dc.subject |
Timing |
en_US |
| dc.subject |
Digital integrated circuits |
en_US |
| dc.subject |
Algorithm design and analysis |
en_US |
| dc.subject |
Monte Carlo methods |
en_US |
| dc.subject |
Random variables |
en_US |
| dc.subject |
Operations research |
en_US |
| dc.title |
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits |
en_US |
| dc.type |
Article |
en_US |