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Study of ZnO/BST interface for thin-film transistor (TFT) applications

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dc.contributor.author Gupta, Navneet
dc.contributor.author Kandpal, Kavindra
dc.contributor.author Shekhar, Chandra
dc.date.accessioned 2023-02-04T06:19:16Z
dc.date.available 2023-02-04T06:19:16Z
dc.date.issued 2021-04
dc.identifier.uri https://www.sciencedirect.com/science/article/pii/S2468023021000730
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8955
dc.description.abstract This work presents an investigation of ZnO/BST interface for the potential use of (Ba,Sr)TiO3 as a gate–dielectric in ZnO based thin-film transistors (TFTs) for low-voltage operation. A metal-insulator-semiconductor capacitor (MIS-C) structure, which consists of a Pt/BST/ZnO stack, was fabricated on a corning glass substrate. The capacitance-voltage (C-V) characteristic of MIS-C gives the capacitance peak in both forward and backward sweep. This peak behavior of BST is due to its paraelectric nature attributed by changing the direction of a polar molecule over the applied electric field. C-V curve of ZnO/BST MIS-C structure exhibits a counter-clockwise hysteresis of -1.33 V due to the existence of donor-like oxygen vacancies present in BST and ZnO interface. The subthreshold slope of the device was found to be 203 mV/ decade and calculated using the measurement of interface state density (Dit). ZnO/BST interface also exhibits a very low value of leakage current density (3.148 × 10−7 Acm−2). Thus, the use of BST as a gate-dielectric in ZnO TFT has excellent potential, owing to its steep subthreshold slope, which implies fast switching and low off-state current. en_US
dc.language.iso en en_US
dc.publisher Elsevier en_US
dc.subject EEE en_US
dc.subject ZnO TFT en_US
dc.subject MIS-C en_US
dc.subject Interface trap density (Dit) en_US
dc.subject Hysteresis en_US
dc.subject SPICE Level-3 en_US
dc.title Study of ZnO/BST interface for thin-film transistor (TFT) applications en_US
dc.type Article en_US


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